With the recent increase in the densities of the semiconductor devices, the sizes of circuit patterns of LSIs constituting the semiconductor devices are further reduced. In order to reduce the sizes of the patterns, it is necessary to not only reduce line widths but also improve the dimensional and positional accuracies of the patterns.
A storage device called a memory is not the exception. It is desired to maintain a specified number of charges required for storage in a smaller area in a cell formed using an accurate patterning technique.
Various semiconductor memories such as DRAMs, SRAMs, and flash memories have hitherto been manufactured. However, all of these memories employ MOSFETs as memory cells, so that the reduction in the size of the pattern is accompanied by a demand for an increase in the dimensional accuracy by a rate larger than that by which the size of the pattern is reduced.
Thus, a heavy burden has also been imposed on a lithography technique for forming these patterns. This in turn has increased the cost of a lithography process accounting for the major part of the present mass production cost, that is, the product cost.
On the other hand, in order to solve these problems, a memory called ReRAM (Resistive Random Access Memory) has been recently suggested. In the ReRAM, a memory cell is constituted by a nonohmic element such as a diode and a resistance change element.
The ReRAM can be achieved without using accumulated charges for storing information and without using MOSFETs for memory cells. Therefore, the ReRAM is expected to achieve a higher density than the density of the past trend.
By the way, in a diode used for a memory cell of the ReRAM, a tolerable value of a current flowing in a forward direction and a tolerable value of a leak current flowing in a backward direction need to respectively satisfy a certain standard based on the a property of a resistance change element. However, when the density increases, and the sizes of the memory cells are reduced, it is necessary to solve many technical problems in order to satisfy the certain standard.
For example, when a cell size (a size where a planar shape is assumed to be a square) is several dozen nanometers by several dozen nanometers, a large current of 1 μA or more is needed in a reset operation in which the memory cell changes from a low resistance state to a high resistance state.
A carrier scattering increases at the same time, which increases the loss, when the tolerable value of the current flowing in the forward direction is increased by increasing an atom density of an n-type impurity in an n−-type semiconductor area (cathode) of a diode in order to satisfy the standard.
On the other hand, when the diode is used as a selection element, this kind of reset operation is preferably performed with a small loss. However, in order to flow a large current through the diode with a small loss during the reset operation, it is necessary to reduce the atom density of the n-type impurity in the n−-type semiconductor area of the diode so as to reduce the carrier scattering of the current flowing in the forward direction.
In other words, the tolerable value of the current flowing in the forward direction and the loss caused by the carrier scattering are a tradeoff with regard to the atom density of the n-type impurity of the n−-type semiconductor area of the diode, and it is difficult to improve both of the tolerable value of the current flowing in the forward direction and the loss caused by the carrier scattering at the same time.